Trends in terrestrial neutron-induced soft-errors in SRAMs down to 22 nm process are predicted by using the Monte- Carlo simulator CORIMS. The following results are obtained. One, Soft-error rates per device in SRAMs will increase x6-7 from 130 nm to 22 nm process. Two, as SRAM is scaled down to a smaller size, SEU is dominated more significantly by low energy neutrons (< 10 MeV). Three, the area affected by one nuclear reaction spreads well beyond 1 M bits area and the multiplicity of multi-cell upset become as high as 100 bits and more. 5Instead of using traditional way to increase the critical charge required to flip a cross-coupled feedback mechanism, we presented a dynamic memory-based solution, lacking internal feedback, which utilizes CDMR and single-bit parity to achieve per-bit error detection and single bit error correction capabilities. The proposed 4T CDMR memory array was implemented in a 65-nm technology within a silicon footprint that is 47% smaller than a conventional 6-T SRAM bit cell and 2.5×–5× smaller than other state of- the-art radiation-hardened bit cells. In addition, the static power consumption of the proposed topology is more than 48% lower than the other soft-error tolerant bit cells across the entire operating range. 8 The 10T SRAM cell that reduces soft errors by 98% and use to access read operation. The Differential read is very critical for easier design of the sense amplifier and for reliable sense operation under the worst case conditions. This 10T SRAM cell offering better data stability compared to the 6T cell as well as the DICE cell. In addition, the cell can be used as a latch to design soft error robust register files and flip-flops.