The author Rana Alhalabi (2017) 28 discussed that Speed of memory access lowers the execution speed in FPGAs and the overall function is effected by large amount of data. To overcome this problem a nonvolatile Look up table based on Spin transfer torque magnetic RAM (STT-RAM) is employed. This nvLUT is also capable of handling large number of inputs. The overall area is significantly reduced by implemented N-MOS based pass gates. The power consumption is reduced up to 46%, and speed delay is reduced up to 55%, and density area of 47% reduced is for the designed FPGA based system.
The authors Safeen Huda (2017) 27 discussed that, Routing power in FPGAs is increased significantly due to the routing resources, as the occupy most of the FPGA Area. The authors defines that dynamic power can be controlled by identifying routing conductors that are not in use and static power can by reduced by observing leakage in routing multiplexers. To optimize total power consumption in routing network CAD tools are used. Results shows that dynamic and static power are reduced up to 25% and 81% respectively and delay speed of ?10% with delay overhead over of area-overhead of 2.6%–4.8%.
The author Zahra Ebrahimi (2017) 23 discussed about the SRAM FPGA based architectures. For existing and future technologies Logic integration in FPGA becomes restricted due to increase in static power. Authors proposed an FPGA Architecture which is efficient in power. It is based on combination of three input LUT with reconfigurable hard logic with soft logic. Authors use power gating technique in which Static power of logic blocks is minimized by turning off inactive hard and soft logic elements.In response, the 24.5% Static Power, dynamic power 39.7 % and speed delay of 21.3% with approx. 19% area is reduced using the proposed technique.
The author Sonda CHTOUROU (2017) 21 Performed Overall analysis to minimize Power, Area and delay tradeoffs. Authors introduced a novel architecture by joining mesh and hierarchical topologies. They employed butterfly fat tree (BFT) topology which based on unoccupied routing interconnection. By implementing proposed architecture authors conclude that: Power dissipation, delay, and area are 205nw, 55.255(ns) and 17500(E+6?2) respectively with optimum cluster size is 8 and LUT size is 4. The area density of 17500 (E+6?2) with Best cluster size 8 and LUT size 4 is achieved using the proposed technique.